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HT82A523R i/o type usb 8-bit otp mcu with spi rev. 1.10 1 february 22, 2008 general description this device is an 8-bit high performance risc-like microcontroller designed for usb product applications. it is particularly suitable for use in products such as usb mouse or keyboard and supports interface for finger- print controller. a halt feature is included to reduce power consumption. features operating voltage: f sys =6mhz & 12mhz: 3.3v~5.5v 40 bidirectional i/o lines (max.) one 16-bit programmable timer/event counter with overflow interrupt one 8-bit programmable timer/event counter with overflow interrupt only crystal oscillator (6mhz or 12mhz) watchdog timer 4096 15 program memory rom 192 8 data memory ram halt function and wake-up feature reduce power consumption 6-level subroutine nesting 2 sets of sio (synchronous serial i/o) function supports interrupt, control, bulk transfer usb 2.0 full speed function compatible 4 endpoints supported (endpoint 0 included) total fifo size is 152 bytes (8, 8, 8, 64 2 for ep0~ep3) bit manipulation instruction 15-bit table read instruction 63 powerful instructions all instructions in one or two machine cycles low voltage reset function 32-pin lqfp package 48-pin ssop package 52-pin qfp package technical document tools information faqs application note
block diagram HT82A523R rev. 1.10 2 february 22, 2008

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pin assignment pin description pin name i/o options description pa0/psync, pa1~pa7 i/o pull-high (bit option) wake-up (bit option) i/o or psync bi-directional 8-bit input/output port. each bit can be configured as a wake-up input by rom code option. the input or output mode is controlled by pac (pa control register, bit option). pull-high resistor options: pa0~pa7, bit option, wake up options: pa0~pa7 (pa0~pa3 support falling edge wake-up only, pa4~pa7 support both rising and falling edge wake-up) the psync is pin-shared with pa0 (dependent on psync option) pb0/clk, pb1~pb7 i/o pull-high (bit option) cmos/nmos wake-up (nibble option) i/o or clk bidirectional 8-bit input/output port. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (determined by pull-high options: bit option). cmos/nmos options: pb0~pb7. wake up options: pb0~pb7 (pb0~pb7 support falling edge wake-up). the clk is pin-shared with pb0 (dependent on clk option) and the fre - quency of the clk output is the same as system clock. pc0/int pc1/tmr0 pc2/tmr1 pc3 pc4/scs2 pc5/sck2 pc6/sdi2 pc7/sdo2 i/o pull-high (nibble option) wake-up (nibble option) bidirectional i/o lines. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (determined by pull high options, nibble option). the int , tmr0, tmr1 are pin-shared with pc0, pc1, pc2 respectively. the scs2 is pin-shared with pc4. scs2 is serial interface chip select pin, master mode is output, slave mode is input. the sck2 is pin-shared with pc5. sck2 is serial interface serial clock in - put/output (slave/master, initial is input). the sdi2 is pin-shared with pc6. sdi2 is serial interface serial input. the sdo2 is pin-shared with pc7. sdo2 is serial interface serial output. wake up options: pc0~pc7(pc0~pc7 support falling edge wake-up) pd0~pd7 i/o pull-high (nibble option) wake-up (nibble option) bidirectional i/o lines. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). wake-up options: pd0~pd7(pd0~pd7 support falling edge wake-up) HT82A523R rev. 1.10 3 february 22, 2008

pin name i/o options description pe0/scs pe1/sck pe2/sdi pe3/sdo pe4~pe7 i/o pull-high (nibble option) wake-up (nibble option) bidirectional i/o lines. software instructions determine the cmos output or schmitt trigger input with pull-high resistor (determined by pull-high options: nibble option). the pe0 is pin-shared with scs . scs is a chip select pin of the serial inter - face, master mode is output, slave mode is input. the pe1 is pin-shared with sck. sck is a serial interface serial clock in - put/output (initial is input). the pe2 is pin-shared with sdi. sdi is serial interface serial input. the pe3 is pin-shared with sdo. sdo is a serial interface serial output. wake up options: pe0~pe7(pe0~pe7 support falling edge wake-up) res i schmitt trigger reset input, active low vss negative power supply, ground avss adc negative power supply, ground vdd positive power supply vddio positive power supply, vddio is used for pa, pb, pc, pd and pe. avdd adc positive power supply, avdd should be externally connected to vdd. osc1 osc2 i o osc1 and osc2 are connected to a 6mhz or 12mhz crystal/resonator (de - termined by software instructions) for the internal system clock. v33o o 3.3v regulator output, can be disabled by firmware. udp i/o udp is usbd+ line usb function is controlled by software control register. udn i/o udn is usbd- line usb function is controlled by software control register. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT82A523R rev. 1.10 4 february 22, 2008
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =6mhz or 12mhz 3.3 5.5 v v ddio operating voltage for i/o ports 3.0 5.5 v i dd1 operating current (6mhz crystal) 5v no load, f sys =6mhz 6.5 12 ma i dd2 operating current (12mhz crystal) 5v no load, f sys =12mhz 7.5 16 ma i stb1 standby current 5v no load, system halt, usb suspend 300 500 a i stb2 standby current 5v no load, system halt, input/output mode, set susp2 [22h].4 20 a v il1 input low voltage for i/o ports 0 0.3v ddio v v ih1 input high voltage for i/o ports 0.7v ddio v ddio v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v i ol i/o port sink current v ol =0.33v 25 ma i oh i/o port source current v oh =v ddio 0.33v 2 5 ma r ph pull-high resistance v ddio =0.33v 20 60 100 k v lvr low voltage reset voltage 2.0 2.2 2.4 v v 33o 3.3v regulator output 5v i v33o =5ma 3.0 3.3 3.6 v a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (crystal osc) 5v 400 12000 khz f timer timer i/p frequency (tmr0/tmr1) 5v 0 12000 khz t wdtosc watchdog oscillator period 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period power-up, reset or wake-up from halt 1024 *t sys t int interrupt pulse width 1 s note: *t sys =1/f sys HT82A523R rev. 1.10 5 february 22, 2008
HT82A523R rev. 1.10 6 february 22, 2008 functional description execution flow the system clock is derived from either a crystal or an rc oscillator. it is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and ex - ecution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. the pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. if an instruction changes the value of the program counter, two cycles are required to com - plete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a full range of program memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the pc manipulates the program transfer by loading the address corre - sponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed to the next instruction. the lower byte of the program counter (pcl) is a read - able and write able register (06h). moving data into the pcl performs a short jump. the destination will be within the current program rom page. when a control transfer takes place, an additional dummy cycle is required. mode program counter *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 000000000000 external interrupt 000000000100 timer/event counter 0 overflow 000000001000 timer/event counter 1 overflow 000000001100 usb interrupt 000000010000 serial interface interrupt 000000010100 serial interface 2 interrupt 000000011000 skip program counter+2 loading pcl *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *11~*0: program counter bits s11~s0: stack register bits #11~#0: instruction code bits @7~@0: pcl bits 2 ( 2 ( 2 ( / # * * 9 : ; * * 9 1 : / # * * 9 0 : ; * * 9 : / # * * 9 0 : ; * * 9 0 : 0 0 * + < * 9 * + : execution flow
HT82A523R rev. 1.10 7 february 22, 2008 program memory eprom the program memory (eprom) is used to store the pro - gram instructions which are to be executed. it also con - tains data, table, and interrupt entries, and is organized into 4096 15 bits which are addressed by the program counter and table pointer. certain locations in the rom are reserved for special usage: location 000h location 000h is reserved for program initialization. after a chip reset, the program always begins execu - tion at this location. location 004h location 004h is reserved for the external interrupt service program. if the int input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. location 008h location 008h is reserved for the timer/event coun - ter 0 interrupt service program. if a timer interrupt re - sults from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the pro - gram begins execution at location 008h. location 00ch location 00ch is reserved for the timer/event coun- ter 1 interrupt service program. if a timer interrupt re- sults from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the pro- gram begins execution at location 00ch. location 010h location 010h is reserved for the usb interrupt ser- vice program. if the usb interrupt is activated, the in- terrupt is enabled and the stack is not full, the program begins execution at location 010h. location 014h location 014h is reserved for 8 bits data have been received or transmitted successful from serial inter - face , and the related interrupts are enabled, and the stack is not full, the program begins execution at loca - tion 014h. location 018h location 018h is reserved for 8 bits data have been received or transmitted successful from serial inter - face 2, and the related interrupts are enabled, and the stack is not full, the program begins execution at loca - tion 018h. table location any location in the program memory can be used as a look-up tables. there are three methods to read the rom data using two table read instructions tabrdc and tabrdl , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). the three methods are shown as follows: the instruction tabrdc [m] (the current page, one page=256 words), where the table location is defined by tblp (07h) in the current page. the configuration option, tbhp, is disabled (default). the instructions tabrdc [m] , where the table lo - cation is defined by registers tblp (07h) and tbhp (01fh). the configuration option, tbhp, is enabled. the instruction tabrdl [m] , where the table lo - cations is defined by registers tblp (07h) in the last page (0f00h~0fffh). + * $ * * * =
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HT82A523R rev. 1.10 8 february 22, 2008 only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are trans - ferred to the lower portion of tblh. the table higher-order byte register (tblh) is read only and can - not be restored. the table pointer (tblp, tbhp) is a read/write register (07h, 1fh), which indicates the table location. before accessing the table, the location must be placed in the tblp and tbhp registers(if the config - uration option tbhp is disabled, the value in tbhp has no effect). if the main routine and the isr (interrupt service rou - tine) both employ the table read instruction, the contents of the tblh in the main routine is likely to be changed by the table read instruction used in the isr. as a result er - rors may occur. in other words, using the table read in - struction in the main routine and in the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main rou - tine and the isr, the interrupt should be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending on the require - ments. once tbhp is enabled, the instruction tabrdc [m] reads the rom data as defined by tblp and tbhp reg- ister value. otherwise, if the configuration option tbhp is disabled, the instruction tabrdc [m] reads the rom data as defined by tblp and the current program counter bits. stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither read - able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or an interrupt acknowledgment, the contents of the program counter are pushed onto the stack. at the end of the subroutine or an interrupt rou - tine, signaled by a return instruction (ret or reti), the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt is serviced. this feature prevents stack overflow, allowing the programmer to use the structure more easily. if the stack is full and a call is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 6 return addresses are stored). data memory ram the data memory (ram) is designed with 235 8 bits, + * *
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HT82A523R rev. 1.10 9 february 22, 2008 and is divided into two functional groups, namely; spe - cial function registers (43 8 bits) and general purpose data memory (192 8 bits) most of which are read - able/writeable, although some are read only. the unused space before 40h is reserved for future ex - panded usage and reading these locations will get 00h . the general purpose data memory, addressed from 40h to ffh, is used for data and control informa - tion under instruction commands. all of the data mem - ory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer regis - ters (mp0;01h/mp1;03h). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] accesses the ram pointed to by mp0 (01h) and mp1 (03h) respectively. reading lo - cation 00h or 02h indirectly returns the result 00h. while, writing into it, indirectly leads to no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the ram by combining corresponding indirect addressing registers. accumulator acc the accumulator is closely related to alu operations. it is also mapped to location 05h of the ram and capable of operating with immediate data. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operations. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz, etc.) the alu not only saves the results of a data operation but also changes the status register. status register status the status register (0ah) is 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pdf), and a watchdog time-out flag (to). it also records the status in - formation and controls the operation sequence. except for the to and pdf flags, bits in the status register can be altered by instructions similar to other registers. data written into the status register does not alter the to or pdf flags. operations related to the status register, how - ever, may yield different results from those intended. the to and pdf flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the watchdog timer and executing the halt instruction. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or exe- cuting a subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero, otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise ov is cleared. 4 pdf pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register
HT82A523R rev. 1.10 10 february 22, 2008 interrupts this device provides external interrupts (int pin inter - rupt, a/d converter interrupt, serial interface interrupt) and internal timer/event counter interrupts. the interrupt control register0 (intc0;0bh) and interrupt control register1 (intc1:1eh) both contain the interrupt control bits that are used to set the enable/disable status and in - terrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc0 or intc1 may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. external interrupts can are triggered by a falling edge transition of int ), and the related interrupt request flag (eif; bit4 of the intc0) is set as well. after the interrupt is enabled, the stack is not full, and the external interrupt is active (int pin), a subroutine call at location 04h oc - curs. the interrupt flag (eif) and emi bits are all cleared to disable other maskable interrupts. the internal timer/event counter 0 interrupt is initialized by setting the timer/event counter 0 interrupt request flag (bit 5 of the intc0), caused by a timer 0 overflow. when the interrupt is enabled, the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be reset and the emi bit cleared to disable further interrupts. the internal timer/event counter 1 interrupt is initialized by setting the timer/event counter 1 interrupt request flag (bit 6 of the intc0), caused by a timer 1 overflow. when the interrupt is enabled, the stack is not full and the t1f is set, a subroutine call to location 0ch will occur. the related interrupt request flag (t1f) will be reset and the emi bit cleared to disable further interrupts. usb interrupts are triggered by the following usb events and the related interrupt request flag (usbf; bit 4 of the intc1) will be set. the access of the corresponding usb fifo from pc the usb suspend signal from the pc the usb resume signal from the pc usb reset signal bit no. label function 0 emi controls the master (global) interrupt (1= enable; 0= disable) 1 eei controls the external interrupt (1= enable; 0= disable) 2 et0i controls the timer/event counter 0 interrupt (1= enable; 0= disable) 3 et1i controls the timer/event counter 1 interrupt (1= enable; 0= disable) 4 eif external interrupt request flag (1= active; 0= inactive) 5 t0f internal timer/event counter 0 request flag (1= active; 0= inactive) 6 t1f internal timer/event counter 1 request flag (1= active; 0= inactive) 7 unused bit, read as 0 intc0 (0bh) register bit no. label function 0 eui control the usb interrupt (1= enable; 0= disable) 1 esii control serial interface interrupt (1= enabled; 0= disabled) 2 es2ii control serial interface 2 interrupt (1= enabled; 0= disabled) 3, 7 unused bit, read as 0 4 usbf usb interrupt request flag (1= active; 0= inactive) 5 sif serial interface interrupt request flag (1= active; 0= inactive) 6 si2f serial interface 2 interrupt request flag (1= active; 0= inactive) intc1 (1eh) register
HT82A523R rev. 1.10 11 february 22, 2008 when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to loca - tion 10h will occur. the interrupt request flag (usbf) and emi bits will be cleared to disable other interrupts. when pc host access the fifo of the HT82A523R, the corresponding request bit of usr is set, and a usb in - terrupt is triggered when the corresponding interrupt is enabled. so user can easily determine which fifo is accessed. when the interrupt has been served, the cor - responding bit should be cleared by firmware. when the HT82A523R receives a usb suspend signal from the host pc, the suspend line (bit0 of the usc) of the HT82A523R is set and a usb interrupt is also triggered. also when the HT82A523R receives a resume signal from the host pc, the resume line (bit3 of the usc) of the HT82A523R is set and a usb interrupt is triggered. whenever a usb reset signal is detected, a usb inter - rupt is triggered. the serial interface interrupt is indicating by the interrupt flag (sif: bit 5 of intc1 or si2f: bit 6 of intc1), that is caused by received or transferred a complete 8-bit data between HT82A523R and external device. the serial in - terface interrupt is controlled by setting the serial inter - face interrupt control bit (esii: bit 1 of intc1 or esi2i: bit2 of intc1). after the interrupt is enabled (by setting sben; bit 4 of sbcr or sbcr2), and the stack is not full and the sif is set, a subroutine call to location 14h or 18h occurs. during the execution of an interrupt subroutine, other in- terrupt acknowledge signals are held until the reti in- struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch usb interrupt 4 10h serial interface interrupt 5 14h serial interface 2 interrupt 6 18h it is recommended that a program does not use the call subroutine within the interrupt subroutine. inter - rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con - trolled, the original control sequence will be damaged once the call operates in the interrupt subroutine. oscillator configuration there is an oscillator circuit in the microcontroller. this oscillator is designed for system clocks. the halt mode stops the system oscillator and ignores an exter - nal signal to conserve power. a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator. no other external components are required. instead of a crystal, a resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters a power down mode and the system clock is stopped, but the wdt oscillator still works. the wdt oscillator can be disabled by rom code option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys- tem clock divided by 4) determined by options. this timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpre - dictable results. the watchdog timer can be disabled by options. if the watchdog timer is disabled, all executions related to the wdt results in no operation. once an internal wdt oscillator (rc oscillator with a pe - riod of 65 s, normally at 5v) is selected, it is divided by 2 12 ~2 16 (by option to get the wdt time-out period). the wdt time-out minimum period is about 300ms. this time-out period may vary with temperature, vdd and process variations. by selection from the wdt option, longer time-out periods can be realized. if the wdt time-out is selected as 2 15 ~2 16 , the maximum time-out period is divided by 2 15 which about 2.3s. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operates in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by external logic. if the device operates in a noisy environment, us - ing the on-chip rc oscillator (wdt osc) is strongly rec - ommended, since the halt will stop the system clock. + * + + system oscillator
HT82A523R rev. 1.10 12 february 22, 2008 the wdt overflow under normal operation will initialize a chip reset and set the status bit to. whereas in the halt mode, the overflow will initialize a warm reset and only the program counter and stack pointer are re - set to zero. to clear the contents of wdt, three methods are adopted; external reset (a low level to res ), soft - ware instructions, or a halt instruction. the software instructions include clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruc - tion, only one can be active depending on the option clr wdt times selection option .ifthe clr wdt is selected (i.e. clrwdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case clr wdt1 and clr wdt2 are chosen (i.e. clrwdt times equal two), these two instructions must be executed to clear the wdt, otherwise, the wdt may reset the chip due to time-out. power down operation halt the halt mode is initialized by the halt instruction and results in the following: the system oscillator is turned off but the wdt oscil- lator keeps running (if the wdt oscillator or the real time clock is selected). the contents of the on-chip ram and registers remain unchanged. the wdt will be cleared and start recounting (if the wdt clock source is from the wdt oscillator or the real time clock). all of the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can quit the halt mode in many ways, by an external reset, an interrupt (except serial interface inter - rupt and serial interface 2 interrupt), an external falling edge or rising edge signal on i/o ports or a wdt over - flow. an external reset causes a device initialization and the wdt overflow performs a warm reset . after exam - ining the to and pdf flags, the cause for a chip reset can be determined. the pdf flag is cleared by a system power-up or by executing the clr wdt instruction and is set when executing the halt instruction. on the other hand, the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer; and leaves the others in their original status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device by option. awakening from an i/o port stimulus, the program will resume execution of the next instruc - tion. if it awakens from an interrupt, two sequences may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. but if the interrupt is enabled and the stack is not full, a regular interrupt re - sponse takes place. when an interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be disabled. if a wake-up event occurs, it takes 1024 f sys (system clock period) to resume normal operation. in other words, a dummy period is inserted after wake-up. if the wake-up results from an interrupt acknowledge, the actual inter- rupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next in- struction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset may occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and stack pointer, leav - ing the other circuits in their original state. some regis - ters remain unaffected during any other reset conditions. most registers are reset to the initial condi - tion when the reset conditions are met. examining the pdf and to flags, the program can distinguish between different chip resets . $ ) ' 7 * + < ' ( a ! ) * +
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HT82A523R rev. 1.10 13 february 22, 2008 to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up at halt 1 u wdt time-out during normal operation 1 1 wdt wake-up at halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem awakes from the halt state or during power up. awaking from the halt state or system power up, an sst delay is added. an extra sst delay is added during power up period, and any wake-up from halt may en - able only the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler, divider cleared wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack ) * ) @ " + ! > 1 * - 1 = * + ) ; + 1 reset configuration 0 * 1 # * * reset timing chart - - < - < - . / d - . - / d reset circuit note: * make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference. the registers states are summarized in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu status --00 xxxx --1u uuuu --uu uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 tmr0 xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
HT82A523R rev. 1.10 14 february 22, 2008 register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 00-0 1000 00-0 1000 tmr1h xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pe 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pec 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 clk 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 intc1 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 tbhp xxxx xxxx 0000 uuuu 0000 uuuu 0000 uuuu 0000 uuuu 0000 uuuu 0000 uuuu usc 1-00 0000 u-uu uuuu 1-00 0000 1-00 0000 u-uu uuuu u-00 0100 u-00 0100 usr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ucc -000 0000 -uuu uuuu -000 0000 -000 0000 -uuu uuuu -uu0 u000 -uu0 u000 awr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stall ---- 1110 ---- uuuu ---- 1110 ---- 1110 ---- uuuu ---- 1110 ---- 1110 sies 0100 0000 uuuu uuuu 0100 0000 0100 0000 uuuu uuuu 0100 0000 0100 0000 misc 0xx- -000 uxx- -uuu 0xx- -000 0xx- -000 uxx- -uuu 000- -000 000- -000 setio ---- 1110 ---- uuuu ---- 1110 ---- 1110 ---- uuuu ---- 1110 ---- 1110 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 sbcr 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu uuuu uuuu uuuu uuuu sbdr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu sbcr2 0110 0000 0110 0000 0110 0000 0110 0000 uuuu uuuu uuuu uuuu uuuu uuuu sbdr2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown
HT82A523R rev. 1.10 15 february 22, 2008 timer/event counter two timer/event counters (tmr0, tmr1) are imple - mented in the microcontroller. the timer/event counter 0 contains a 8-bit programmable count-up counter and the clock may come from an external source or an inter - nal clock source. an internal clock source comes from f sys . the timer/event counter 1 contains a 16-bit pro - grammable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys /4. the external clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base. there are five registers related to the timer/event counter 0; tmr0 (0dh), tmr0c (0eh) and the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). for 16bits timer to write data to tmr1l will only put the written data to an internal lower-order byte buffer (8-bit) and writing tmr1h will transfer the specified data and the contents of the lower-order byte buffer to tmr1h and tmr1l registers. the timer/event counter 1 preload register is changed by each writing tmr1h operations. reading tmr1h will latch the con - tents of tmr1h and tmr1l counters to the destination and the lower-order byte buffer, respectively. reading the tmr1l will read the contents of the lower-order byte buffer. the tmr0c (tmr1c) is the timer/event coun- ter 0 (1) control register, which defines the operating mode, counting enable or disable and an active edge. the t0m0, t0m1 (tmr0c) and t1m0, t1m1 (tmr1c) bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external (tmr0, tmr1) pin. the timer mode functions as a normal timer with the clock source coming from the internal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external sig - nal (tmr0, tmr1), and the counting is based on the in - ternal selected clock source. in the event count or timer mode, the timer/event coun - ter starts counting at the current contents in the timer/event counter and ends at ffffh (for 16 bits timer is ffffh, bit 8 bits timer will be ffh). once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re - quest flag (t0f; bit 5 of the intc0, t1f; bit 6 of the intc0). in the pulse width measurement mode with the values of the t0on/t1on and t0e/t1e bits equal to 1, after the tmr0 (tmr1) has received a transient from low to high (or high to low if the t0e/t1e bit is 0 ), it will start count - ing until the tmr0 (tmr1) returns to the original level and resets the t0on/t1on. the measured result re - mains in the timer/event counter even if the activated transient occurs again. in other words, only 1-cycle measurement can be made until the t0on/t1on is set. the cycle measurement will re-function as long as it re- ceives further transient pulse. in this operation mode, -
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HT82A523R rev. 1.10 16 february 22, 2008 the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt re - quest, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit (t0on: bit 4 of the tmr0c; t10n: bit 4 of the tmr1c) should be set to 1. in the pulse width measurement mode, the t0on/t1on is automatically cleared after the measurement cycle is completed. but in the other two modes, the t0on/t1on can only be reset by in - structions. the overflow of the timer/event counter 0/1 is one of the wake-up sources. no matter what the oper - ation mode is, writing a 0 to et0i or et1i disables the re - lated interrupt service. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also re - loads that data to the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter is kept only in the timer/event coun - ter preload register. the timer/event counter still contin - ues its operation until an overflow occurs. when the timer/event counter (reading tmr0/tmr1) is read, the clock is blocked to avoid errors, as this may re - sults in a counting error. blocking of the clock should be taken into account by the programmer. it is strongly rec - ommended to load a desired value into the tmr0/tmr1 register first, before turning on the related timer/event counter, for proper operation since the initial value of tmr0/tmr1 is unknown. due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. after this procedure, the timer/event function can be operated normally. bit no. label function 0~2 unused bit, read as 0 3 t0e defines the tmr active edge of the timer/ event counter (0=active on low to high; 1=active on high to low) 4 t0on enable/disable timer counting (0=disable; 1=enable) 5 unused bit, read as 0 6 7 t0m0 t0m1 defines the operating mode, t0m1, t0m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh) register bit no. label function 0~2, 5 unused bit, read as 0 3 t1e defines the tmr active edge of the timer/ event counter (0=active on low to high; 1=active on high to low) 4 t1on enable/disable timer counting (0=disable; 1=enable) 6 7 t1m0 t1m1 defines the operating mode, t1m1, t1m0: 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr1c (11h) register
HT82A523R rev. 1.10 17 february 22, 2008 input/output ports there are 40 bidirectional input/output lines in the microcontroller, labeled from pa to pe, which are mapped to the data memory of [12h], [14h], [16h], [18h] and [1a] respectively. all of these i/o ports can be used for input and output operations. for input opera - tion, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h, 18h or 1a). for output oper - ation, all the data is latched and remains unchanged un - til the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc, pec) to control the input/output configura - tion. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. to function as an input, the corresponding latch of the control register must write a 1 . the input source also depends on the control register. if the control register bit is 1 the input will read the pad state. if the control reg - ister bit is 0 the contents of the latches will move to the internal bus. the latter is possible in the read-mod - ify-write instruction. for output function, cmos is the only configuration (except pb can be configured as cmos output or nmos output). these control registers are mapped to locations 13h, 15h, 17h, 19h and 1bh. pa0 is pin-shared with psync signal (dependent on psync option, the rising edge of psync is used to syn - chronize the sbdr data of the serial interface which is pin-shared with port e). pb0 is pin-shared with clk signal (dependent on clk option). after a chip reset, these input/output lines remain at high levels or floating state (depending on the pull-high op - tions). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h, 16h, 18h or 1ah ) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. all the i/o ports have the capability of waking-up the device. it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state.

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HT82A523R rev. 1.10 18 february 22, 2008 low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications: the low voltage range (0.9v~v lvr ) has to be main - tained for over 1ms, otherwise, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform a chip reset. serial interface serial interface function similar to spi (motorola), has four basic signals included. they are sdi (serial data in - put), sdo (serial data output), sck (serial clock) and scs (slave select pin). there are two serial interfaces. one serial interface is pin-shared with port e, and the other serial interface is pin-shared with port c. two registers (sbcr and sbdr) unique to serial inter - face provide control, status, and data storage. sbcr: serial bus control register bit7 (cks) clock source selection: 0=f sio =f sys /4 1=f sio =f sys bit6 (m1), bit5 (m0) master/slave mode and baud rate selection m1, m0= 00
master mode, baud rate= f sio 01
master mode, baud rate= f sio /4 10
master mode, baud rate= f sio /16 11
slave mode bit4 (sben)
serial bus enable/disable (1/0) enable: (scs dependent on csen bit) disable
enable: sck, sdi, sdo, scs =0 (sckb= 0 ) and waiting for writing data to sbdr (txrx buffer) master mode: write data to sbdr (txrx buffer) start transmission/reception automatically master mode: when data has been transferred, set trf slave mode: when an sck (and scs dependent on csen) is received, data in txrx buffer is shifted-out and data on sdi is shifted-in. disable: sck (sck ), sdi, sdo, scs floating bit3 (mls)
msb or lsb (1/0) shift first control bit bit2 (csen)
serial bus selection signal en - able/disable (scs ), when csen=0, scs is floating. the scs should be pulled high externally to avoid malfunction. bit1 (wcol)
this bit is set to 1 if data is written to sbdr (txrx buffer) when data is transferred, writing will be ignored if data is written to sbdr (txrx buffer) when data is transferred. bit0 (trf)
data transferred or data received used to generate an interrupt. sbdr: serial bus data register data written to sbdr
write data to txrx buffer only data read from sbdr
read from sbdr only operating mode description: master transmitter: clock sending and data i/o started by writing sbdr master clock sending started by writing sbdr slave transmitter: data i/o started by clock received slave receiver: data i/o started by clock received 4 ' - 6 ' 5 ' ( ' 2 2 ' ( ' 5 ' 6 - ' 4 4 ' - 6 ' 5 ' ( ' 2 2 ' ( ' 5 ' 6 - ' 4 " , / " , / " ? * c c * * # ! .

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HT82A523R rev. 1.10 19 february 22, 2008 clock polarity= rising (clk ) or falling (clk): 1 or 0 (mask option) modes operations master 1. select cks and select m1, m0 = 00,01,10 2. select csen, mls (the same as the slave) 3. set sben 4. writing data to sbdr
data is stored in txrx buffer
output clk (and scs ) signals
go to step 5
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data stored in txrx buffer, and sdi data is shifted into txrx buffer
data transferred, data in txrx buffer is latched into sbdr) 5. check wcol; wcol= 1
clear wcol and go to step 4; wcol= 0
go to step 6 6. check trf or waiting for sbi (serial bus interrupt) 7. read data from sbdr 8. clear trf 9. go to step 4 slave 1. cks don t care and select m1, m0= 11 2. select csen, mls (the same as the master) 3. set sben 4. writing data to sbdr
data is stored in txrx buffer
waiting for master clock signal (and scs ): clk
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clk (scs ) received
output data in txrx buffer and sdi data is shifted into txrx buffer
data transferred, data in txrx buffer is latched into sbdr) 5. check wcol; wcol= 1
clear wcol, go to step 4; wcol= 0
go to step 6 6. check trf or wait for sbi (serial bus interrupt) 7. read data from sbdr 8. clear trf 9. go to step 4 operation of serial interface wcol: master/slave mode, set while writing to sbdr when data is transferring (transmitting or receiving) and this writing will then be ignored. wcol function can be enabled/disabled by mask option. wcol is set by sio and cleared by users. data transmission and reception are still working when the mcu enters the halt mode. cpol is used to select the clock polarity of clk. it is a mask option. mls: msb or lsb first selection csen: chip select function enable/disable, csen=1
scs signal function is active. master should output scs signal before clk signal is set and slave data transfer - ring should be disabled (or enabled) before (after) scs signal is received. csen= 0, scs signal is not needed, scs pin (master and slave) should be floating. csen has 2 options: csen mask option is used to enable/dis - able software csen function. if csen mask option is disabled, the software csen is always disabled. if csen mask option is enabled, software csen function can be used. sben= 1
serial bus standby; scs (csen= 1) = 1; scs = floating (csen= 0); sdi= floating; sdo= 1; mas - ter clk= output 1/0 (dependent on cpol mask option), slave clk= floating sben= 0
serial bus disabled; scs = sdi= sdo= clk= floating trf is set by sio and cleared by users. when data transfer (transmission and reception) is completed, trf is set to generate sbi (serial bus interrupt). if the psync option is enabled, use the sync signal to synchronize the sdbr (the next data which the sdbr receives will be bit7). please refer to the following timing (only for the spi interface which is pin-shared with port e.): the sync signal is used to synchronize the sdbr when both the HT82A523R is working under slave mode and psync option is enabled. otherwise, if the HT82A523R is working under master mode, the psync option is ignored and the sync signal is not used to synchronize the sdbr.
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HT82A523R rev. 1.10 21 february 22, 2008 & & dma function dma function is enabled when dma bit of the usb misc register is set to 1. if dma function is enabled, either the sbdr of the serial interface 1 (which is pin-shared with port e) or the sbdr of the serial interface 2 (which is pin-shared with port c) will be written to the fifo3 directly. if sben bit and dma bit are set, the spi interface which is select with dmasel bit will send out the sck clock during master mode. the frequency of the sck is con - trolled by cks & m1 & m0 also. the sck clock output will be stopped automatically when fifo3 is full and will restart automatically when fifo3 is not full. the sck clock will stay at low level if cpol is 1 and stay at high level if cpol is 0 when it is stopped. suspend wake-up or remote wake-up if there is no signal on the signal bus for over 3ms, the HT82A523R will go into suspend mode. the suspend line (bit 0 of the usc) will be set to 1 and a usb interrupt is triggered to indicate that the HT82A523R should jump to suspend state to meet the 500 a usb suspend cur - rent spec. in order to meet the 500 a suspend current, the firm - ware should disable the usb clock by clearing the usbcken (bit3 of the ucc) to 0 . the suspend cur - rent is about 400 a. the user can also further decrease the suspend current by setting the susp2 (bit4 of the ucc). but if the susp2 is set, user should make sure not to enable the lvr opt op - tion, otherwise, the HT82A523R will be reset. if user set the susp2 (bit4 of the ucc) in the usb mode, user must set rctrl (bit7 of the ucc) before set susp2 (bit4 of the ucc), otherwise, usb will disconnected. when the resume signal is sent out by the host, the HT82A523R will wake-up the by usb interrupt and the resume line (bit 3 of the usc) is set. in order to make the HT82A523R work properly, the firmware must set the usbcken (bit 3 of the ucc) to 1 and clear the susp2 (bit4 of the ucc). if user set the rctrl (bit7 of the ucc) and susp2 (bit4 of the ucc) in the usb sus - pend, when it will wake-up user must clr rctrl (bit7 of the ucc) before clr susp2 (bit4 of the ucc). since the re - sume signal will be cleared before the idle signal is sent out by the host and the suspend line (bit 0 of the usc) is going to 0 . so when the mcu is detecting the suspend line (bit0 of usc), the resume line should be remem - bered and taken into consideration. after finishing the resume signal, the suspend line will go inactive and a usb interrupt is triggered. the follow - ing is the timing diagram: the device with remote wake-up function can wake-up the usb host by sending a wake-up pulse through rmwk (bit 1 of the usc). once the usb host receive the wake-up signal from the HT82A523R, it will send a resume signal to the device. the timing is as follow: usb interface the HT82A523R has 4 endpoints (ep0~ep3). ep0~ep2 are support interrupt transfer, ep3 is support bulk transfer. there are 12 registers, including usc (20h), usr (21h), ucc (22h), awr (address+remote wake-up 23h), stall (24h), sies (25h), misc (26h), setio (27h), fifo0 (28h), fifo1 (29h), fifo2 (2ah) and fifo3 (2bh) used for the usb function. , * * + , h , * * + , h
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HT82A523R rev. 1.10 22 february 22, 2008 the fifo size of each fifo is 8 byte (fifo0), 8 byte (fifo1), 8 byte (fifo2) and 128 byte (fifo3), and total of 152 bytes. urd (bit7 of the usc) is usb reset signal control function definition bit. bit no. label r/w function 0 susp r read only, usb suspend indication. when this bit is set to 1 (set by sie), it indicates that the usb bus enters the suspend mode. the usb interrupt is also triggered on any changes of this bit. 1 rmwk r/w usb remote wake-up command. it is set by the mcu to force the usb host leaving the suspend mode. set rmwk bit to 1 to enable remote wake-up. when this bit is set to 1 ,a2 s delay for clearing this bit to 0 is needed to insure that the rmwk command is accepted by the sie. 2 urst r/w usb reset indication. this bit is set/cleared by usb sie. when the urst is set to 1 , this indicates that a usb reset has occurred and a usb interrupt will be initialized. 3 resume r usb resume indication. when the usb leaves the suspend mode, this bit is set to 1 (set by sie). this bit will appear for 20ms, waiting for the mcu to detect it. when the resume is set by sie, an interrupt will be generated to wake-up the mcu. in order to detect the suspend state, mcu should set the usbcken and susp2 (in the scc reg - ister) to enable the sie detect function. the resume will be cleared while the susp is set to 0 . when mcu detects the susp, the resume (which causes mcu to wake-up) should be remembered and token into consideration. 4 v33o r/w 0/1: turn-off/on v33o output 5 pll r/w 0: turn-on the pll (default mode); 1: turn-of the pll 6 undefined bit, read as 0 7 urd r/w usb reset signal control function definition 1: usb reset signal will reset the mcu 0: usb reset signal cannot reset the mcu usc (20h) definitions the usr (usb endpoint interrupt status register) register is used to indicate which endpoint is accessed. the endpoint request flags (ep0if, ep1if, ep2if and ep3if) are used to indicate which endpoints are accessed. if an endpoint is ac- cessed, the related endpoint request flag will be set to 1 and the usb interrupt will occur (if the usb interrupt is en- abled, the corresponding interrupt is enabled and the stack is not full). when the active endpoint request flag is served, the endpoint request flag has to be cleared to 0 . bit no. label r/w function 0 ep0if r/w when this bit is set to 1 (set by sie), it indicates that the endpoint 0 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 1 ep1if r/w when this bit is set to 1 (set by sie), it indicates that the endpoint 1 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 2 ep2if r/w when this bit is set to 1 (set by sie), it indicates that the endpoint 2 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 3 ep3if r/w when this bit is set to 1 (set by sie), it indicates that the endpoint 3 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 4 eep0i r/w control the endpoint 0 interrupt (1=enabled; 0=disable). 5 eep1i r/w control the endpoint 1 interrupt (1=enabled; 0=disable). 6 eep2i r/w control the endpoint 2 interrupt (1=enabled; 0=disable). 7 eep3i r/w control the endpoint 3 interrupt (1=enabled; 0=disable). usr (21h) definitions
HT82A523R rev. 1.10 23 february 22, 2008 there is a system clock control register implemented to select the clock used in the mcu. this register consists of usb clock control bit (usbcken), second suspend mode control bit (susp2) and system clock selection (sysclk) the following table defines which endpoint fifo is selected, eps2, eps1 and eps0. bit no. label r/w function 0 1 2 eps0 eps1 eps2 r/w accessing endpoint fifo selection. eps2, eps1, eps0: 000: select endpoint 0 fifo 001: select endpoint 1 fifo 010: select endpoint 2 fifo 011: select endpoint 3 fifo 100: reserved for future expansion, cannot be used 101: reserved for future expansion, cannot be used 110: reserved for future expansion, cannot be used 111: reserved for future expansion, cannot be used if the selected endpoints do not exist, the related functions are not available. 3 usbcken r/w usb clock control bit. when this bit is set to 1 , it indicates that the usb clock is enabled. otherwise, the usb clock is turned-off. 4 susp2 r/w this bit is used to reduce power consumption in suspend mode. in normal mode, clear this bit to 0 (default) in halt mode, set this bit to 1 to reduce power consumption. 5 f sys (24mhz) r/w this bit is used to define the mcu system clock to come from either the external osc or from pll output 24mhz clock. 0: system clock comes from osc 1: system clock comes from pll output 24mhz 6 sysclk r/w this bit is used to specify the system clock oscillator frequency used by the mcu. if a 6mhz crystal oscillator or resonator is used, this bit should be set to 1 . if a 12mhz crystal oscillator or resonator is used. this bit should be cleared to 0 (default). 7 rctrl r/w this bit is used to control whether there is 7.5k ohm resistor between d+ and vbus 0: no 7.5k between d+ and vbus (default) 1: has 7.5k between d+ and vbus ucc (22h) definitions the awr register contains the current address and the remote wake-up function control bit. the initial value of the awr is 00h . the address value extracted from the usb command is not to be loaded into this register until the setup stage is finished. bit no. label r/w function 0 wken r/w remote wake-up enable/disable (1/0) 1~7 ad0~ad6 r/w usb device address awr (23h) definitions the stall register shows whether the corresponding endpoint works properly or not. as soon as the endpoint works improperly, the related bit in the stall has to be set to 1 . the stall will be cleared by the usb reset signal. bit no. label r/w function 0~3 stl0~ stl3 r/w set by users when the related usb endpoints are stalled. they are cleared by usb reset and setup token event 4~7 undefined bit, read as 0 stall (24h) definitions
HT82A523R rev. 1.10 24 february 22, 2008 bit no. label r/w function 0 aset r/w this bit is used to configure the sie to automatically change the device address with the value stored in the awr register. when this bit is set to 1 by firmware, the sie will update the device address with the value stored in the awr register after the pc host has successfully read the data from the device by in operation. otherwise, when this bit is cleared to 0 , the sie will update the device address immediately af - ter an address is written to the awr register. so, in order to work properly, firmware has to clear this bit after the next valid setup token is received. 1 err r/w this bit is used to indicate there are some errors occurred during the fifo0 is ac - cessed. this bit is set by sie and should be cleared by firmware. 2 out r/w this bit is used to indicate there are out token (except for the out zero length token) that have been received. the firmware clears this bit after the out data has been read. also, this bit will be cleared by sie after the next valid setup token is received. 3inr this bit is used to indicate that the current usb receiving signal from the pc host is in token. (1=in token; 0=non in token) 4 nak r this bit is used to indicate that the sie has transmitted a nak signal to the host in re - sponse to the pc host in or out token. (1=nak signal; 0=non nak signal) 5 crcf r/w error condition failure flag include crc, pid, no integrate token error, crcf will be set by hardware and the crcf need to be cleared by firmware. 6 eot r token package active flag, low active. 7 nmi r/w nak token interrupt mask flag. if this bit is set, when the device sent a nak token to the host, interrupt will not occur. otherwise, when this bit is cleared, and the device sent a nak token to the host, it will enter the interrupt subroutine. the nmi is de - signed for all endpoints. sies (25h) definitions misc register combines a command and status to control the desired endpoint fifo action and to show the status of the desired endpoint fifo. the misc will be cleared by usb reset signal. bit no. label r/w function 0 request r/w after selecting the desired endpoint, fifo can be requested by setting this bit as high active. afterwards, this bit must be set low. 1 tx r/w this indicates the direction and transition end which the mcu accesses. when set as logic 1, the mcu writes data to fifo. afterwards, this bit must be set to logic 0 be - fore terminating request to indicate transition end. for reading action, this bit must be set to logic 0 to indicate that the mcu wants to read and must be set to logic 1 af - terwards. 2 clear r/w this indicates an mcu clear requested fifo, even if the fifo is not ready. after clearing the fifo, usb interface will send force_tx_err to tell host that data un - der-run if host want to read data. 3 dma r/w 1: enable sbdr of the serial interfaces (which is pin-shared with port e or port c) be - ing written to fifo3 directly. 0: disable sbdr of the serial interfaces (which is pin-shared with port e or port c) being written to fifo3 directly. spi interfaces can be controlled by mcu and mcu can transmit or receive data by writing or reading sbdr. it is allowed changing from 1 to 0 when the fifo is not full. 4 dmasel r/w 0: serial interface (pin-shared with port e) uses the dma function. 1: serial interface 2 (pin-shared with port c) uses the dma function. 5 setcmd r/w to show that the data in fifo is setup command. this bit will last this state until next one entering the fifo. (1=setcmd token; 0=non setcmd token) 6 ready r to tell that the desired fifo is ready to work. (1=ready to work; 0=non ready to work) 7 len0 r/w to tell that host sent a 0-sized packet to mcu. this bit must be cleared by read action to corresponding fifo. (1=host sent a 0-sized packet) misc (26h) definitions
HT82A523R rev. 1.10 25 february 22, 2008 there are some timing constrains and usages illustrated here. by setting the misc register, mcu can perform reading, writing and clearing actions. there are some examples shown in the following table for endpoint fifo reading, writing and clearing. actions misc setting flow and status read fifo0 sequence 00h
01h
delay 2 s, check 41h
read* from fifo0 register and check not ready (01h)
03h
02h write fifo0 sequence 02h
03h
delay 2 s, check 43h
write* to fifo0 register and check not ready (03h)
01h
00h check whether fifo0 can be read or not 00h
01h
delay 2 s, check 41h (ready) or 01h (not ready)
00h check whether fifo0 can be written or not 02h
03h
delay 2 s, check 43h (ready) or 03h (not ready)
02h read 0-sized packet sequence form fifo0 00h
01h
delay 2 s, check 81h
read once (01h)
03h
02h write 0-sized packet sequence to fifo0 02h
03h
delay 2 s, check 03h
07h
06h
00h read or write fifo table note: *: there are 2 s existing between 2 reading action or between 2 writing action bit no. label r/w function 0 datatg* r/w to toggle this bit, all the data token will send a data0 first. 1 setio1** r/w set endpoint 1 input or output pile (1/0), default input pipe (1) 2 setio2** r/w set endpoint 2 input or output pile (1/0), default input pipe (1) 3 setio3** r/w set endpoint 3 input or output pile (1/0), default input pipe (1) 4~7 undefined bit, read as 0 setio (27h) register, usb endpoint 1~endpoint3 set in/out pipe register note: *usb definition: when the host sends a set configuration , the data pipe should send the data0 (data tog - gle) first. so, when the device receives a set configuration setup command, user needs to toggle this bit so the next data will send a data0 first. **needs to set the data pipe as an input pile or output pile. the purpose of this function is to avoid the host from abnormally sending only an in or out token and disables the endpoint. label r/w function fifoi r/w epi accessing register (i = 0~3). when an endpoint is disabled, the corresponding accessing register should be disabled. fifo0~fifo03 (28h~2bh) register, usb endpoint accessing registers definitions i . ! ;

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HT82A523R rev. 1.10 26 february 22, 2008 options the following table shows all kinds of options in the microcontroller. all of the otp options must be defined to ensure a proper functioning system. the default values of the options are 0 . no. option 1 pa0~pa7 pull-high resistor enable or disable (by bit) (default non-pull-high) 2 pb0~pb7 pull down resistor enable or disable (by bit) (default non-pull-high) 3 pc0~pc7 pull-high resistor enable or disable (by nibble) (default non-pull-high) 4 pd0~pd7 pull-high resistor enable or disable (by nibble) (default non-pull-high) 5 pe0~pe7 pull-high resistor enable or disable (by nibble) (default non-pull-high) 6 lvr enable or disable (default disable) 7 clk enable or disable (if clk enable then pb0 i/o port will be disable) (default disable) 8 sio (serial interface) enable or disable (if sio is enabled then pe0~pe3 i/o port will be disabled) (default disable) 9 sio2 (serial interface 2) enable or disable (if sio2 enable then pc4~pc7 i/o port will be disable) (default disable), 0=disable; 1=enable 10 sio_ cpol: clock polarity 1/0: clock polarity rising or falling edge (default falling edge) 11 sio_ cpol2: clock polarity 1/0 : clock polarity rising/falling edge (default falling edge 0 ) 0=falling edge 1=rising edge 12 sio_wcol: enable or disable (default disable) 13 sio_wcol2: enable or disable (default disable 0 ) 0=disable; 1=enable 14 sio_csen: enable or disable, csen mask option is used to enable/disable (1/0) software csen function (default disable) 15 sio_csen2: enable or disable, csen mask option is used to enable/disable software csen function (de- fault disable 0 ) 0=disable; 1=enable 16 wdt enable or disable (default disable) 17 wdt clock source: f sys /4 or wdtosc (default wdtosc) 18 wdt timeout period: 2 12 ~2 13 /f s (00), 2 13 ~2 14 /f s (01), 2 14 ~2 15 /f s (10), 2 15 ~2 16 /f s (11) (default 2 12 ~2 13 /f s ) 19 clrwdt instruction (s): 1 or 2 (default 1 instruction) 20 pa0~pa7 wake-up enable or disable (by bit) (default disable) 21 pb0~pb7 wake-up enabled or disabled (by nibble) (default disable) 0= non-wakeup; 1=wake-up 22 pb0~pb7 output structures: cmos/nmos (by bit) (default nmos 0 ) 0=nmos; 1=cmos 23 pc0~pc7 wake-up enabled/disabled (by nibble) (default disable 0 ) 0=non-wakeup; 1=wakeup 24 pd0~pd7 wake-up enabled/disabled (by nibble) (default disable 0 ) 0=non-wakeup; 1=wakeup 25 pe0~pe7 wake-up enabled/disabled (by nibble) (default disable 0 ) 0=non-wakeup; 1=wakeup 26* ep1~ep3 data pipe enable: ep1, ep2, ep3 enable or disable. (default is enable) 27 psync enable/disable (if psync enable then pa0 i/o port will be disable and the rising edge of psync is used to synchronize the sbdr data) (default disable) table high byte pointer for current table read (tbhp) 0=disable; 1=enable note: *: the purpose of this option is to enable the endpoint that will be used, and disable the endpoint that will not be used (usb chapter 8 will test this function).
timing diagram application circuits crystal or ceramic resonator for multiple i/o applications. note: the resistor and capacitor reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before the res line is brought high. x1 can be a 6mhz or 12mhz crystal located as close to the osc1 and osc2 pins as possible the 22pf capacitors are only applied if ceramic resonators are used HT82A523R rev. 1.10 27 february 22, 2008 vdd r/bb cs_vout p_sync f_sync clk mosi adc_dat adc_sy n rst sck sda mcuvdd mcuvdd vddio vdd csb vddio r3 33 r8 10k 6mhz usb con 1 2 3 4 5 vdd usb- usb+ vss shield u1 HT82A523R 1 2 3 4 5 6 7 8 9 10 35 36 37 38 39 40 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 41 42 43 44 45 46 47 48 pa1 pa0/psy nc pd3 pd2 pd1 pd0 pb7 pb6 pb5 pb4 vdd osc2 osc1 resb pd7 pd6 pc7/sdo2 pc6/sdi2 pc5/sck2 pc4/scs2b pb3 pb2 pb1 pb0/clk pe3/sdo pe2/sdi pe1/sck pe0/scsb pc3 pc2/tmr1 pc1/tmr0 pc0/intb avss nc udn udp v33o avdd vddio vss pd5 pd4 pa7 pa6 pa5 pa4 pa3 pa2 u2 ht7533-1 2 3 1 vin vout gnd c7 22pf c8 22pf r6 1m r1 100k c10 470pf c3 0.1uf c2 47uf c1 0.1uf r2 10k c9 0.1uf c5 0.1uf c6 10uf r4 1.5k c12 47pf c4 0.1uf r7 33 c11 47pf r5 33 b b w g r * " - - - 4 6 5 ( 2 - 4 6 5 ( 2 - 4 6 5 ( 2 - 4 6 5 ( 2 -
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HT82A523R rev. 1.10 28 february 22, 2008 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
HT82A523R rev. 1.10 29 february 22, 2008 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
HT82A523R rev. 1.10 30 february 22, 2008 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT82A523R rev. 1.10 31 february 22, 2008
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT82A523R rev. 1.10 32 february 22, 2008
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT82A523R rev. 1.10 33 february 22, 2008
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT82A523R rev. 1.10 34 february 22, 2008
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT82A523R rev. 1.10 35 february 22, 2008
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT82A523R rev. 1.10 36 february 22, 2008
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT82A523R rev. 1.10 37 february 22, 2008
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT82A523R rev. 1.10 38 february 22, 2008
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT82A523R rev. 1.10 39 february 22, 2008
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT82A523R rev. 1.10 40 february 22, 2008
package information 32-pin lqfp (7 7) outline dimensions symbol dimensions in mm min. nom. max. a 8.9 9.1 b 6.9 7.1 c 8.9 9.1 d 6.9 7.1 e 0.8 f 0.35 g 1.35 1.45 h 1.6 i 0.1 j 0.45 0.75 k 0.1 0.2 0 7 HT82A523R rev. 1.10 41 february 22, 2008 5 7 2 , % @ j ( 4 6 8 /
48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 613 637 d85 99 e 25 f4 10 g25 35 h4 12 0 8 HT82A523R rev. 1.10 42 february 22, 2008 ( 7 5 ( , / k % @
52-pin qfp (14 14) outline dimensions symbol dimensions in mm min. nom. max. a 17.3 17.5 b 13.9 14.1 c 17.3 17.5 d 13.9 14.1 e 1 f 0.4 g 2.5 3.1 h 3.4 i 0.1 j 0.73 1.03 k 0.1 0.2 0 7 HT82A523R rev. 1.10 43 february 22, 2008 2 8 ( - 5 4 2 , ( 6 / % @ j
product tape and reel specifications reel dimensions ssop 48w symbol description dimensions in mm a reel outer diameter 330 1 b reel inner diameter 100 0.1 c spindle hole diameter 13+0.5 0.2 d key slit width 2 0.5 t1 space between flange 32.2+0.3 0.2 t2 reel thickness 38.2 0.2 HT82A523R rev. 1.10 44 february 22, 2008 ,
carrier tape dimensions ssop 48w symbol description dimensions in mm w carrier tape width 32 0.3 p cavity pitch 16 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 14.2 0.1 d perforation diameter 2 min. d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4 0.1 p1 cavity to perforation (length direction) 2 0.1 a0 cavity length 12 0.1 b0 cavity width 16.2 0.1 k1 cavity depth 2.4 0.1 k2 cavity depth 3.2 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 25.5 HT82A523R rev. 1.10 45 february 22, 2008 - / , - - )
HT82A523R rev. 1.10 46 february 22, 2008 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, gaoxin m 2nd, middle zone of high-tech industrial park, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2008 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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